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Ultra High CMR, Small Outline, 5 Lead, High Speed Optocoupler Technical Data
HCPL-M454 Features
* Function Compatible with HCPL-4504 * Surface Mountable * Very Small, Low Profile JEDEC Registered Package Outline * Compatible with Infrared Vapor Phase Reflow and Wave Soldering Processes * Short Propagation Delays for TTL and IPM Applications * Very High Common Mode Transient Immunity: Guaranteed 15 kV/s at VCM = 1500 V * High CTR: >25% at 25C * Guaranteed Specifications for Common IPM Applications * TTL Compatible * Guaranteed ac and dc Performance Over Temperature: 0C to 70C * Open Collector Output * Recognized Under the Component Program of U.L. (File No. E55361) for Dielectric Withstand Proof Test Voltage of 3750 Vac. 1 Minute * Lead Free Option "-000E"
Applications
* Inverter Circuits and Intelligent Power Module (IPM) Interfacing - Shorter propagation delays and guaranteed (tPLH - tPHL) specifications. (See Power Inverter Dead Time section). * High Speed Logic Ground Isolation - TTL/TTL, TTL/ LTTL, TTL/CMOS, TTL/ LSTTL
* Line Receivers - High common mode transient immunity (>15 kV/s for a TTL load/ drive) and low input-output capacitance (0.6 pF). * Replace Pulse Transformers - Save board space and weight * Analog Signal Ground Isolation - Integrated photon detector provides improved linearity over phototransistors
Outline Drawing (JEDEC MO-155)
ANODE 1 4.4 0.1 (0.173 0.004)
6
VCC
MXXX XXX
7.0 0.2 (0.276 0.008) CATHODE 3
5 VOUT 4 GND
TYPE NUMBER (LAST 3 DIGITS) 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) 0.102 0.102 (0.004 0.004) 0.15 0.025 (0.006 0.001) DATE CODE
2.5 0.1 (0.098 0.004)
1.27 BSC (0.050)
0.71 MIN. (0.028) MAX. LEAD COPLANARITY = 0.102 (0.004)
DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
CAUTION: The small junction sizes inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
2
Description
The HCPL-M454 is similar to Agilent's other high speed transistor output optocouplers, but with shorter propagation delays and higher CTR. The HCPL-M454 also has a guaranteed propagation delay difference (tPLH - tPHL). These features make the HCPL-M454 an excellent solution to IPM inverter dead time and other switching problems.
The HCPL-M454 CTR, propagation delays, and CMR are specified both for TTL load and drive conditions and for IPM (Intelligent Power Module) load and drive conditions. Specifications and typical performance plots for both TTL and IPM conditions are provided for ease of application. This diode-transistor optocoupler uses an insulating layer between
the light emitting diode and an integrated photon detector to provide electrical insulation between input and output. Separate connections for the photodiode bias and output transistor collector increase the speed up to a hundred times over that of a conventional phototransistor coupler by reducing the base-collector capacitance.
Absolute Maximum Ratings
(No Derating Required up to 85C) Storage Temperature .................................................... -55C to +125C Operating Temperature ................................................ -55C to +100C Average Input Current - IF ......................................................... 25 mA[1] Peak Input Current - IF .............................................................. 50 mA[2] (50% duty cycle, 1 ms pulse width) Peak Transient Input Current - IF ................................................... 1.0 A (1 s pulse width, 300 pps) Reverse Input Voltage - VR (Pin 3-1) .................................................. 5 V Input Power Dissipation ........................................................... 45 mW[3] Average Output Current - IO (Pin 5) ............................................... 8 mA Peak Output Current .................................................................... 16 mA Output Voltage - VO (Pin 5-4)............................................ -0.5 V to 20 V Supply Voltage - VCC (Pin 6-4) .......................................... -0.5 V to 30 V Output Power Dissipation ....................................................... 100 mW [4] Infrared and Vapor Phase Reflow Temperature ....................... see below
Solder Reflow Thermal Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
3
Recommended Pb-Free IR Profile
TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC.
tp Tp TL 260 +0/-5 C 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C
TEMPERATURE
Tsmax Tsmin
RAMP-DOWN 6 C/SEC. MAX.
ts PREHEAT 60 to 180 SEC. 25 t 25 C to PEAK
tL
60 to 150 SEC.
TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C
Schematic
ICC 6 VCC
Land Pattern Recommendation
4.4 (0.17)
+ ANODE 1 VF CATHODE - 3
IF
2.5 (0.10) 1.3 (0.05)
IO
5
VO
SHIELD
4 GND
2.0 (0.080) 8.27 (0.325) DIMENSION IN MILLIMETERS (INCHES)
0.64 (0.025)
Insulation Related Specifications
Parameter Minimum External Air Gap (Clearance) Minimum External Tracking Path (Creepage) Minimum Internal Plastic Gap (Clearance) Tracking Resistance Isolation Group (per DIN VDE 0109) Symbol L(IO1) L(IO2) Value 5 5 0.08 CTI 175 IIIa Units mm mm mm V Conditions Measured from input terminals to output terminals Measured from input terminals to output terminals Through insulation distance conductor to conductor DIN IEC 112/VDE 0303 Part 1 Material Group DIN VDE 0109
4
DC Electrical Specifications
Over recommended temperature (TA = 0C to 70C) unless otherwise specified. (See note 11) Parameter Symbol Min. Typ. Max. Units Current Transfer Ratio Current Transfer Ratio Logic Low Output Voltage Logic High Output Current CTR 25 21 CTR 26 22 VOL 32 34 35 37 0.2 0.2 IOH 0.003 0.01 0.4 0.5 0.5 1.0 50 Logic Low Supply Current Logic High Supply Current Input Forward Voltage Input Reverse Breakdown Current Temperature Coefficient of Forward Voltage Input Capacitance InputOutput Insulation Voltage Resistance (InputOutput) Capacitance (InputOutput) ICCL 50 200 A IF = 16 mA VCC = 15 V VO = open 11 A V 65 % 60 % Test Conditions TA = 25C VO = 0.4 V VO = 0.5 V TA = 25C VO = 0.4 V VO = 0.5 V TA = 25C IO = 3.0 mA IO = 2.4 mA Fig. Note IF = 16 mA 1,2,4 VCC = 4.5 V IF = 12 mA 1,2,4 VCC = 4.5 V IF = 16 mA VCC = 4.5 V 5 5 5
TA = 25C VO = VCC = 5.5 V IF = 0 mA TA = 25C VO = VCC = 15 V
ICCH
0.02 0.02
1 2 1.7 1.8
A
TA = 25C IF = 0 mA VO = open TA = 25C IF = 16 mA
VCC = 15 V
11
VF
1.5 1.5
V
3
BVR
5
V
IR = 10 A
VF /TA
-1.6
mV/C IF = 16 mA
CIN VISO 3750
60
pF VRMS
f = 1 MHz VF = 0 V RH < 50% TA = 25C t = 1 min 6,12
RI-O
10[12]
VI-O = 500 Vdc
6
CI-O
0.6
pF
f = 1 MHz
6
5
Switching Specifications
Over recommended temperature (TA = 0C to 70C) unless otherwise specified Parameter Propagation Delay Time to Logic Low at Output Sym. tPHL Min. Typ. Max. Units Test Conditions 0.2 0.3 s TA = 25C Pulse: f = 20 kHz Duty Cycle = 10% 0.2 0.5 IF = 16 mA VCC = 5.0 V RL = 1.9 k CL = 15 pF VTHHL = 1.5 V 0.2 0.1 0.5 0.5 0.7 1.0 TA = 25C Pulse: f = 10 kHz Duty Cycle = 50% IF = 12 mA VCC = 15.0 V RL = 20 k CL = 100 pF VTHHL = 1.5 V s TA = 25C Pulse: f = 20 kHz Duty Cycle = 10% IF = 16 mA VCC = 5.0 V RL = 1.9 k CL = 15 pF VTHLH = 1.5 V TA = 25C Pulse: f = 10 kHz Duty Cycle = 50% IF = 12 mA VCC = 15.0 V RL = 20 k CL = 100 pF VTHLH = 2.0 V s TA = 25C Pulse: f = 10 kHz Duty Cycle = 50% IF = 12 mA VCC = 15.0 V RL = 20 k CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V Fig. Note 8, 9 9
1014
10
Propagation Delay Time to Logic High at Output
tPLH
0.3 0.3
0.5 0.7
8, 9
9
0.3 0.2
0.8 0.8
1.1 1.4
1014
10
Propagation Delay Difference Between Any 2 Parts Common Mode Transient Immunity at Logic High Level Output Common Mode Transient Immunity at Logic Low Level Output
tPLHtPHL
-0.4 -0.7
0.3 0.3
0.9 1.3
1014
13
| H| CM
15
30
kV/s TA = 25C VCC = 5.0 V RL = 1.9 k CL = 15 pF IF = 0 mA VCM = 1500 VP-P TA = 25C VCC = 15.0 V RL = 20 k CL = 100 pF IF = 0 mA VCM = 1500 VP-P kV/s TA = 25C VCC = 5.0 V RL = 1.9 k CL = 15 pF IF = 16 mA VCM = 1500 VP-P TA = 25C VCC = 15.0 V RL = 20 k CL = 100 pF IF = 12 mA VCM = 1500 VP-P TA = 25C VCC = 15.0 V RL = 20 k CL = 100 pF IF = 16 mA VCM = 1500 VP-P
7
7,9
15
30
7
8,10
| L| CM
15
30
7
7,9
10
30
7
8,10
15
30
7
8,10
6
Notes: 1. Derate linearly above 70C free-air temperature at a rate of 0.8 mA/C. 2. Derate linearly above 70C free-air temperature at a rate of 1.6mA/C. 3. Derate linearly above 70C free-air temperature at a rate of 0.9 mA/C. 4. Derate linearly above 70C free-air temperature at a rate of 2.0 mA/C. 5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO), to the forward LED input current (IF), times 100. 6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together. 7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM /dt on the leading edge of the common mode
pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable dVCM /dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM /dt on the trailing edge of the
common mode pulse signal,VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V). 9. The 1.9 k load represents 1 TTL unit load of 1.6 mA and the 5.6 k pull-up resistor. 10. The RL = 20 k, CL = 100 pF load represents an IPM (Intelligent Power Mode) load. 11. Use of a 0.1 F bypass capacitor connected between pins 4 and 6 is recommended. 12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, Ii-e 5 A). 13. The difference between tPLH and tPHL, between any two HCPL-M454 parts under the same test condition. (See Power Inverter Dead Time and Propagation Delay Specifications section).
NORMALIZED CURRENT TRANSFER RATIO
35 mA 30 mA 25 mA
IF - FORWARD CURRENT - mA
IO - OUTPUT CURRENT - mA
TA = 25C 10 VCC = 5.0 V
40 mA
1.5
1000 100 10 1.0 0.1 0.01 0.001 1.1
IF + VF -
TA = 25C
1.0
5
20 mA 15 mA 10 mA IF = 5 mA
0.5
0
NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25C 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IF - INPUT CURRENT - mA
0
10 VO - OUTPUT VOLTAGE - V
20
0.0
1.2
1.3
1.4
1.5
1.6
VF - FORWARD VOLTAGE - VOLTS
Figure 1. DC and Pulsed Transfer Characteristics.
Figure 2. Current Transfer Ratio vs. Input Current.
Figure 3. Input Current vs. Forward Voltage.
NORMALIZED CURRENT TRANSFER RATIO
IOH - LOGIC HIGH OUTPUT CURRENT - nA
1.1 1.0
10 4 10 3 10 2 10 1 10 0 10 -1 10-2 -60 -40 -20
IF = 0 mA VO = VCC = 5.0 V
0.9 NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25C
0.8
0.7
0.6 -60 -40 -20 0
20 40 60 80 100 120
0
20 40 60 80 100 120
TA - TEMPERATURE - C
TA - TEMPERATURE - C
Figure 4. Current Transfer Ratio vs. Temperature.
Figure 5. Logic High Output Current vs. Temperature.
7
HCPL-M454 IF 0 VO VTHHL VCC PULSE GEN. ZO = 50 tr = 5 ns IF 1 6 RL 5 VTHLH VOL tPHL tPLH IF MONITOR RM 3 4 0.1F CL VO VCC
Figure 6. Switching Test Circuit.
HCPL-M454 VCM 0V tr 10 V 10% 90% 90% 10% tf VCC SWITCH AT A: IF = 0 mA VO SWITCH AT B: IF = 12 mA, 16 mA VOL + 3 VFF VCM - PULSE GEN. 4 CL A B 5 0.1F IF 1 6 RL VO VCC
VO
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
0.50
tp - PROPAGATION DELAY - s
tPLH
tp - PROPAGATION DELAY - s
0.8 0.6 0.4 0.2 0.0 t PHL IF = 10 mA IF = 16 mA
tPLH
tp - PROPAGATION DELAY - s
VCC = 5.0 V 0.45 RL = 1.9 k CL = 15 pF 0.40 V THHL = VTHLH = 1.5 V 10% DUTY CYCLE 0.35 t PHL 0.30 0.25 0.20 0.15 0.10 -60 -40 -20 0 IF = 10 mA IF = 16 mA
1.4
VCC = 5.0 V T = 25 C 1.2 A CL = 15 pF 1.0 VTHHL = VTHLH = 1.5 V 10% DUTY CYCLE
20 40 60 80 100 120
0
2
4
6
8 10 12 14 16 18 20
2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
VCC = 5.0 V TA = 25 C CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V 50% DUTY CYCLE t PLH IF = 10 mA IF = 16 mA
t PHL
0
2
4
6
8 10 12 14 16 18 20
TA - TEMPERATURE - C
RL - LOAD RESISTANCE - k
RL- LOAD RESISTANCE - k
Figure 8. Propagation Delay Time vs. Temperature.
Figure 9. Propagation Delay Time vs. Load Resistance.
Figure 10. Propagation Delay Time vs. Load Resistance.
8
1.1
tp - PROPAGATION DELAY - s
tp - PROPAGATION DELAY - s
t PLH
50% DUTY CYCLE
t PLH
tp - PROPAGATION DELAY - s
VCC = 15.0 V 1.0 RL = 20 k CL = 100 pF 0.9 V THHL = 1.5 V VTHLH = 2.0 V 0.8 0.7 0.6 0.5 tPHL 0.4 0.3 -60 -40 -20 0
IF = 10 mA IF = 16 mA
1.8
VCC = 15.0 V 1.6 TA = 25 C CL = 100 pF 1.4 VTHHL = 1.5 V 1.2 VTHLH = 2.0 V 50% DUTY CYCLE 1.0 0.8 0.6 0.4 0.2 0.0 0 IF = 10 mA IF = 16 mA t PHL
3.5
VCC = 15.0 V 3.0 TA = 25 C RL = 20 k 2.5 VTHHL = 1.5 V VTHLH = 2.0 V 2.0 50% DUTY CYCLE 1.5 1.0 0.5 0.0
0 200 400
t PLH
t PHL
IF = 10 mA IF = 16 mA
600 800 1000
20 40 60 80 100 120
5 10 15 20 25 30 35 40 45 50 RL - LOAD RESISTANCE - k
TA - TEMPERATURE - C
RL - LOAD CAPACITANCE - pF
Figure 11. Propagation Delay Time vs. Temperature.
Figure 12. Propagation Delay Time vs. Load Resistance.
Figure 13. Propagation Delay Time vs. Load Capacitance.
1.2
tp - PROPAGATION DELAY - s
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 t PHL t PLH
TA = 25 C RL = 20 k CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V 50% DUTY CYCLE
IF = 10 mA IF = 16 mA
0.2 10 11 12 13 14 15 16 17 18 19 20 VCC - SUPPLY VOLTAGE - V
Figure 14. Propagation Delay Time vs. Supply Voltage.
9
+HV + HCPL-M454 6
LED 1
1 5 3 OUT 1 4 BASE/GATE DRIVE CIRCUIT Q1
+ HCPL-M454 6
LED 2
1 5 3 OUT 2 4 BASE/GATE DRIVE CIRCUIT Q2
-HV
Figure 15. Typical Power Inverter.
LED 1
OUT 1
tPLH MIN. tPLH MAX.
(tPLH MAX. - tPLH MIN.)
TURN ON DELAY (tPLH MAX. - tPLH MIN.)
LED 2
OUT 2
tPHL MIN. (tPHL MAX. - tPHL MIN.) tPHL MAX. MAXIMUM DEAD TIME
Figure 16. LED Delay and Dead Time Diagram.
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Power Inverter Dead Time and Propagation Delay Specifications
The HCPL-M454 includes a specification intended to help designers minimize "dead time" in their power inverter designs. The new "propagation delay difference" specification (tPLH tPHL) is useful for determining not only how much optocoupler switching delay is needed to prevent "shoot-through" current, but also for determining the best achievable wort-case dead time for a given design. When inverter power transistors switch (Q1 and Q2 in Figure 15), it is essential that they never conduct at the same time. Extremely large currents will flow if there is any overlap in their conduction during switching transitions, potentially damaging the transistor and even the surrounding circuitry. This "shoot-through" current is eliminated by delaying the turn-on of one transistor (Q2) long enough to ensure that the opposing transistor (Q1) has completely turned off. This delay introduces a small amount of "dead time" at the output of the inverter during which both transistors are off during switching transitions. Minimizing this dead time is an important design goal for an inverter designer. The amount of turn-on delay needed depends on the propagation delay characteristics of the optocoupler, as well as the characteristics of the transistor base/gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the base/gate drive circuit can be analyzed in
the same way), it is important to know the minimum and maximum turn-on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The importance of these specifications is illustrated in Figure 16. The waveforms labeled "LED1", "LED2", "OUT1", and "OUT2" are the input and output voltages of the optocoupler circuits driving Q1 and Q2 respectively. Most inverters are designed such that the power transistor turns on when the optocoupler LED turns on; this ensures that both power transistors will be off in the event of a power loss in the control circuit. Inverters can also be designed such that the power transistor turns off when the optocoupler LED turns on; this type of design, however, requires additional fail-safe circuitry to turn off the power transistor if an over-current condition is detected. The timing illustrated in Figure 16 assumes that the power transistor turns on when the optocoupler LED turns on. The LED signal to turn on Q2 should be delayed enough so that an optocoupler with the very fastest turn-on propagation delay (tPHLmin) will never turn on before an optocoupler with the very slowest turn-off propagation delay (tPLHmax) turns off. To ensure this, the turn-on of the optocoupler should be delayed by an amount no less than (tPLHmax - tPHLmin), which also happens to be the maximum data sheet value for the propagation delay difference specification, (tPLH - tPHL). The HCPL-M454 specifies a maximum (tPLH - tPHL) of 1.3 s over an operating temperature range of 070C.
Although (tPLH - tPHL)max tells the designer how much delay is needed to prevent shoot-through current, it is insufficient to tell the designer how much dead time a design will have. Assuming that the optocoupler turn-on delay is exactly equal to (tPLH - tPHL)max, the minimum dead time is zero (i.e., there is zero time between the turn-off of the very slowest optocoupler and the turn-on of the very fastest optocoupler). Calculating the maximum dead time is slightly more complicated. Assuming that the LED turn-on delay is still exactly equal to (tPLH - tPHL)max, it can be seen in Figure 16 that the maximum dead time is the sum of the maximum difference in turn-on delay plus the maximum difference in turnoff delay, [(tPLHmax-tPLHmin) + (tPHLmaxtPHLmin)], This expression can be rearranged to obtain [(tPLHmax-tPHLmin) - (tPHLmintPHLmax)], and further rearranged to obtain [(tPLH-tPHL)max - (tPLH-tPHL)min], which is the maximum minus the minimum data sheet values of (tPLH - tPHL). The difference between the maximum and minimum values depends directly on the total spread of
11
propagation delays and sets the limit on how good the worst-case dead time can be for a given design. Therefore, optocouplers with tight propagation delay specifications (and not just shorter delays or lower pulsewidth distortion) can achieve
short dead times in power inverters. The HCPL-M454 specifies a minimum (tPLH - tPHL) of -0.7 s over an operating temeprature range of 0-70C, resulting in a maximum dead time of 2.0 s when the LED turn-on delay is equal to (tPLH - tPHL)max, or 1.3 s.
It is important to maintain accurate LED turn-on delays because delays shorter than (tPLH - tPHL)max may allow shootthrough currents, while longer delays will increase the worst-case dead time.
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152 (Domestic/International), or 0120-61-1280 (Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2004 Agilent Technologies, Inc. Obsoletes 5989-0793EN December 28, 2004 5989-2116EN

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